The present invention relates to a synchronizing circuit applied to a semiconductor integrated circuit, such as a synchronous DRAM or a synchronous SRAM, which operates in synchronism with, for example, a clock signal.
In general, a semiconductor integrated circuit for outputting data in synchronism with an external clock signal has a synchronizing circuit therein. This synchronizing circuit controls an output circuit in synchronism with an external clock signal or an internal clock signal having the same period as an external clock signal. As a result, data is output from the output circuit.
FIG. 15 schematically shows the configuration of a data output section of a conventional semiconductor integrated circuit. Data Dout read out from, for example, a memory cell array which is not illustrated is supplied to an output pad 2 via an off-chip driver circuit (hereafter referred to as OCD circuit) 1 serving as an output buffer disposed in a peripheral portion of the semiconductor integrated circuit. This OCD circuit 1 is formed of, for example, a tri-state buffer circuit and logic gates, and driven according to a data output start signal outputted from a synchronizing circuit 3.
The synchronizing circuit 3 has, for example, an input terminal of an internal clock signal CLK, an output terminal of the data output start signal, and terminals X1 and X0 for connection to a replica circuit 4. The replica circuit 4 has, for example, the same configuration as that of the OCD circuit 1 and has a delay time equal to that of the OCD circuit 1. In the synchronizing circuit 3, the internal clock signal CLK is quickened in phase by a delay time set in the replica circuit 4, and outputted as the data output start signal. Therefore, the OCD circuit 1 can output data Dout to the output pad 2 in synchronism with the external clock signal.
In a semiconductor integrated circuit using the above described synchronizing circuit, a P-channel MOS transistor and an N-channel MOS transistor included in the OCD circuit 1 sometimes do not coincide in current drive capability because of dispersion of the fabrication process or the like. In some cases, therefore, the drive capability for data of the high level "H" and the drive capability for data of the low level "L" become unbalanced.
FIG. 16 shows the case where the current drive capability of an N-channel MOS transistor of, for example, a final stage included in the OCD circuit 1 has become greater than the current drive capability of a P-channel MOS transistor. If the current drive capability of the N-channel MOS transistor differs from the current drive capability of the P-channel MOS transistor, then the time required since the data output start signal is activated until the high level output voltage VDout becomes a predetermined level differs from the time required until the low level output voltage VDout becomes a predetermined level. In other words, in this case, it takes a longer time to output high level data than low level data. Therefore, the output voltage VDout of the OCD circuit 1 includes jitter depending upon data of the high level or low level. The jitter has a length of at most approximately 100 ps. As the signal frequency increases, however, its influence becomes great, resulting in a problem.
As described above, the data output start signal is compensated for the delay time in the OCD circuit as compared with the external clock signal. In the conventional technique, however, only the delay for the high level data is compensated. As for the low level data, it is set to the center condition (standard condition) of the process, and compensation for dispersion of the process is not especially conducted. Therefore, there is considered a circuit for compensating jitter in high level data and low level data.
FIG. 17 shows a circuit in which a start signal of the case where high level data is outputted from the OCD circuit is made different from a start signal of the case where low level data is outputted from the OCD circuit. In other words, a synchronizing circuit 5 for generating a start signal of the case where high level data is outputted and a synchronizing circuit 6 for generating a start signal of the case where low level data is outputted are connected to the OCD circuit 1. In the synchronizing circuit 5, for example, a replica circuit 5a of the OCD circuit for outputting low level data is provided. In the synchronizing circuit 6, for example, a replica circuit 6a of the OCD circuit for outputting high level data is provided. When outputting the high level data and the low level data, data output start signals according to the delays of the OCD circuit 1 are thus used, respectively. As a result, jitter of VDout of the high level data and the low level data can be dissolved.
In the case of the circuit shown in FIG. 17, two synchronizing circuits are needed in order to generate the start signal of the case where high level data is outputted and start signal of the case where low level data is outputted. Therefore, there occurs a problem that the area occupied by the synchronizing circuit in the semiconductor integrated circuit becomes great and large power consumption is required.